There is an increasing trend to integrate more floating-point hardware on the main data processor chip. While on-chip integration of floating-point hardware is desirable, limitations of available chip area on high-performance data processors present implementation obstacles. Although integer and floating point division occur infrequently in data processors, divide operations are difficult to pipeline and typically have long latencies. Consequently, in many data processors a significant performance degradation occurs as a result of such data processor performing a divide operation. Furthermore, most data processing systems employ co-processors to perform faster floating-point division, while the main data processor performs the integer divide operations. Thus, today's data processors are generally characterized by slow divide performance, and specifically by slow integer divide performance. This phenomenon is attributable to the fact that faster floating-point divide performance exists primarily in co-processors, but not on single-chip data processors, and not for integer divides.